268 lines
15 KiB
C
268 lines
15 KiB
C
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#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
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#define _ENV_PHYSICAL_SINGLE_CORE_H
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#include "encoding.h"
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//-----------------------------------------------------------------------
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// Begin Macro
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//-----------------------------------------------------------------------
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#define RVTEST_RV64U \
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.macro init; \
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.endm
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#define RVTEST_RV64UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV64UV \
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.macro init; \
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RVTEST_VECTOR_ENABLE; \
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.endm
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#define RVTEST_RV32U \
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.macro init; \
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.endm
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#define RVTEST_RV32UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV32UV \
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.macro init; \
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RVTEST_VECTOR_ENABLE; \
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.endm
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#define RVTEST_RV64M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV64S \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#define RVTEST_RV32M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV32S \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#if __riscv_xlen == 64
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
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#else
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
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#endif
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#define INIT_XREG \
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li x1, 0; \
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li x2, 0; \
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li x3, 0; \
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li x4, 0; \
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li x5, 0; \
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li x6, 0; \
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li x7, 0; \
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li x8, 0; \
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li x9, 0; \
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li x10, 0; \
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li x11, 0; \
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li x12, 0; \
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li x13, 0; \
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li x14, 0; \
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li x15, 0; \
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li x16, 0; \
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li x17, 0; \
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li x18, 0; \
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li x19, 0; \
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li x20, 0; \
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li x21, 0; \
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li x22, 0; \
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li x23, 0; \
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li x24, 0; \
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li x25, 0; \
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li x26, 0; \
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li x27, 0; \
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li x28, 0; \
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li x29, 0; \
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li x30, 0; \
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li x31, 0;
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#define INIT_PMP \
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la t0, 1f; \
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csrw mtvec, t0; \
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/* Set up a PMP to permit all accesses */ \
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li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \
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csrw pmpaddr0, t0; \
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li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
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csrw pmpcfg0, t0; \
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.align 2; \
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1:
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#define INIT_SATP \
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la t0, 1f; \
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csrw mtvec, t0; \
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csrwi satp, 0; \
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.align 2; \
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1:
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#define DELEGATE_NO_TRAPS \
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csrwi mie, 0; \
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la t0, 1f; \
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csrw mtvec, t0; \
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csrwi medeleg, 0; \
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csrwi mideleg, 0; \
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.align 2; \
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1:
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#define RVTEST_ENABLE_SUPERVISOR \
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li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
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csrs mstatus, a0; \
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li a0, SIP_SSIP | SIP_STIP; \
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csrs mideleg, a0; \
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#define RVTEST_ENABLE_MACHINE \
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li a0, MSTATUS_MPP; \
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csrs mstatus, a0; \
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#define RVTEST_FP_ENABLE \
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li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
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csrs mstatus, a0; \
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csrwi fcsr, 0
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#define RVTEST_VECTOR_ENABLE \
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li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
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(MSTATUS_FS & (MSTATUS_FS >> 1)); \
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csrs mstatus, a0; \
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csrwi fcsr, 0; \
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csrwi vcsr, 0;
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#define RISCV_MULTICORE_DISABLE \
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csrr a0, mhartid; \
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1: bnez a0, 1b
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#define EXTRA_TVEC_USER
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#define EXTRA_TVEC_MACHINE
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#define EXTRA_INIT
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#define EXTRA_INIT_TIMER
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#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
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#define RVTEST_CODE_BEGIN \
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.section .text.init; \
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.align 6; \
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.weak stvec_handler; \
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.weak mtvec_handler; \
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.globl _start; \
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_start: \
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/* reset vector */ \
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j reset_vector; \
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.align 2; \
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trap_vector: \
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/* test whether the test came from pass/fail */ \
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csrr t5, mcause; \
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li t6, CAUSE_USER_ECALL; \
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beq t5, t6, write_tohost; \
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li t6, CAUSE_SUPERVISOR_ECALL; \
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beq t5, t6, write_tohost; \
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li t6, CAUSE_MACHINE_ECALL; \
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beq t5, t6, write_tohost; \
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/* if an mtvec_handler is defined, jump to it */ \
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la t5, mtvec_handler; \
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beqz t5, 1f; \
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jr t5; \
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/* was it an interrupt or an exception? */ \
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1: csrr t5, mcause; \
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bgez t5, handle_exception; \
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INTERRUPT_HANDLER; \
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handle_exception: \
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/* we don't know how to handle whatever the exception was */ \
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other_exception: \
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/* some unhandlable exception occurred */ \
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1: ori TESTNUM, TESTNUM, 1337; \
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write_tohost: \
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sw TESTNUM, tohost, t5; \
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j write_tohost; \
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reset_vector: \
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INIT_XREG; \
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RISCV_MULTICORE_DISABLE; \
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INIT_SATP; \
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INIT_PMP; \
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DELEGATE_NO_TRAPS; \
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li TESTNUM, 0; \
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la t0, trap_vector; \
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csrw mtvec, t0; \
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CHECK_XLEN; \
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/* if an stvec_handler is defined, delegate exceptions to it */ \
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la t0, stvec_handler; \
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beqz t0, 1f; \
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csrw stvec, t0; \
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li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
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(1 << CAUSE_STORE_PAGE_FAULT) | \
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(1 << CAUSE_FETCH_PAGE_FAULT) | \
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(1 << CAUSE_MISALIGNED_FETCH) | \
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(1 << CAUSE_USER_ECALL) | \
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(1 << CAUSE_BREAKPOINT); \
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csrw medeleg, t0; \
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1: csrwi mstatus, 0; \
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init; \
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EXTRA_INIT; \
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EXTRA_INIT_TIMER; \
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la t0, 1f; \
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csrw mepc, t0; \
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csrr a0, mhartid; \
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mret; \
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1:
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//-----------------------------------------------------------------------
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// End Macro
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//-----------------------------------------------------------------------
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#define RVTEST_CODE_END \
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unimp
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//-----------------------------------------------------------------------
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// Pass/Fail Macro
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//-----------------------------------------------------------------------
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#define RVTEST_PASS \
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fence; \
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li TESTNUM, 1; \
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li a7, 93; \
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li a0, 0; \
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ecall
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#define TESTNUM gp
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#define RVTEST_FAIL \
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fence; \
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1: beqz TESTNUM, 1b; \
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sll TESTNUM, TESTNUM, 1; \
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or TESTNUM, TESTNUM, 1; \
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li a7, 93; \
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addi a0, TESTNUM, 0; \
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ecall
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//-----------------------------------------------------------------------
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// Data Section Macro
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//-----------------------------------------------------------------------
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#define EXTRA_DATA
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#define RVTEST_DATA_BEGIN \
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EXTRA_DATA \
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.pushsection .tohost,"aw",@progbits; \
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.align 6; .global tohost; tohost: .dword 0; \
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.align 6; .global fromhost; fromhost: .dword 0; \
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.popsection; \
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.align 4; .global begin_signature; begin_signature:
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#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
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#endif
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